In digital electronic circuits, buffers are circuits that receive a digital input signal on an input and develop a digital output signal on an output in response to the input signal. The function of a buffer is typically to isolate logic circuitry supplying the digital input signal to the input of the buffer from a capacitive load coupled to the output of the buffer. The logic circuitry is not typically designed to drive a large capacitive load and thus, if coupled directly to such a load, a long delay may result in driving a voltage across the load to a desired level.
A bidirectional buffer is a buffer circuit that may be programmed or configured to operate either in a first direction or a second direction. Typically, a bidirectional buffer is formed by a pair of cross-coupled buffers that operate in the first direction to drive a signal on a first node in response to a signal on a second node. Conversely, the cross-coupled buffers operate in the second direction to drive a signal on the second node in response to a signal on the first node. Such a bidirectional buffer has memory elements that are utilized to control the direction of operation of the buffer. Each bidirectional buffer includes two memory elements, each memory element being associated with a respective one of the cross-coupled buffers. Each memory element stores data to either enable or disable the corresponding buffer and thereby set the direction of operation of the bidirectional buffer. For example, when each memory element stores a first logic state the corresponding buffer is activated, and when the memory element stores a second logic state the buffer is placed in a high impedance state or disabled. In operation, data having complementary logic states is stored in the memory elements to activate the buffers in the desired direction, or, alternatively, the second logic state is stored in both memory elements to disable both buffers. Note the first logic state is not typically be stored in both memory elements since in this case both buffers would be activated, as will be appreciated by those skilled in the art.
Bidirectional buffers are commonly utilized in programmable integrated circuits, such as field programmable gate arrays (FPGAs), to interconnect functional components within the circuit as required. FIG. 1 is functional block diagram illustrating a portion of a conventional programmable integrated circuit 100 including a number of bidirectional buffers 102a–e, with each buffer including an associated pair of memory cells MC that store data to program the direction of operation of the buffer. A first programmable switch 104 is coupled in series with the buffers 102a, 102b between a first node A and a second node B, where nodes A and B represent either input or output connections to other functional circuitry (not shown) in the integrated circuit 100. A programming logic circuit 106 applies configuration signals 108 to the programmable switch 104 which, in response to these signals, couples selected pairs of the buffers 102a, 102b, and 102e together. In the example of FIG. 1, the switch 104 couples buffer 102a to buffer 102e as indicated by the solid line in the switch.
A second programmable switch 110 is coupled in series with the buffers 102c, 102d between nodes C and D and operates in the same way as the switch 104 to couple selected pairs of the buffers 102c, 102d, 102e together responsive to the signals 108. The switch 110 couples the buffer 102e to the buffer 102d in the example of FIG. 1. Thus, in FIG. 1 node A is coupled to node D through buffer 102a, switch 104, buffer 102e, switch 110, and buffer 102d, with either node A being the input or output depending on the direction of operation of these buffers as determined by the data stored in the corresponding memory cells MC.
In operation, the programming logic 106 receives input signals 112 which would typically include the configuration data for each buffer 102 in form of data to be stored in the associated memory cells MC of the buffer. In response to the input signals 112, the programming logic 106 develops the configuration signals 108 to transfer the configuration data into all the memory cells MC to thereby configure the buffers 102. The programming logic 106 also develops the configuration signals 108 to program the switches 104 using corresponding configuration data.
The programming logic 106 typically transfers the configuration data into the memory cells MC of each buffer 102 in one of two ways. In a first approach, the memory cells MC are serially connected (not shown) and the programming logic 106 applies reset, clocking, and data signals to sequentially shift configuration data into a first pair of memory cells MC and then from pair to pair of memory cells until each pair of memory cells stores the required configuration data. In a second approach, the programming logic 106 includes addressing circuitry (not shown) and the input signals 112 include configuration data and address information for each pair of memory cells MC. With this approach, the programming logic 106 applies reset, address, data, and control signals to the memory cells MC to store the desired configuration data in each pair of memory cells.
In both of these conventional approaches to loading configuration data into the memory cells MC, a significant amount of circuitry may needed to form the programming logic 106, thus consuming valuable space in the integrated circuit 100 that could otherwise be utilized for other functionality. Moreover, each of these approaches requires a significant number of physical lines be routed to provide the signals 108 to each of the memory cells MC and transfer the configuration data into the memory cells. For example, as previously mentioned with the first approach where the memory cells MC are serially connected, the signals 108 must include reset, clocking, and data signals routed to the memory cells. The second approach requires even more physical lines for the signals 108 be routed to the memory cells MC to perform the required reset, addressing, and data transfer to the cells, and the programming logic 106 would typically be more complicated and thus require more circuitry in this approach.
There is a need for configuring bidirectional buffers in an integrated circuit in a way that simplifies programming logic on the chip required to perform such configuration and simplifies the routing of configuration lines to each buffer that are required for configuration.